Digital phase-locked loop circuits have been in use as FM demodulators and may be used in any application in which it is desired to synchronize an input data stream with an external clock. Examples of such circuits are shown in "Analysis and Synthesis of a Digital Phase Locked Loop for FM Demodulation," Pasternack and Whalin, The Bell System Technical Journal, December 1968, pages 2207-2237 and "Jitter Reduction of a Digital Phase Locked Loop," Yamashita el al., Proceedings of the IEEE, November 1976, pages 1640, 1641. A problem with digital phase-locked loops is the presence of noise in the input data stream which may be interpreted as data. If registers or counters are used in the phase detector, the noise will be interpreted as data which is out of phase with the output of a voltage controlled oscillator. It would be desirable to filter this noise from the input data stream while at the same time locking an external clock to the input data stream.